1. Field of the Invention
This invention relates to a recording and reproducing apparatus, and is suitably applied to a recording and reproducing apparatus in which, for example, a recording error is detected when video data is recorded.
2. Description of the Related Art
As this kind of recording and reproducing apparatus, a digital video tape recorder (DVTR) shown in FIG. 1 has been produced. That is, in FIG. 1, 1 generally shows DVTR. An input digital video signal S1 inputted from a predetermined video signal generation unit is inputted to a shuffling circuit 2. The shuffling circuit 2 divides digital video data which is inputted as a digital video signal into discrete cosine transform (DCT) blocks of 8 columns by 4 rows for each field, and then gathers ten blocks of this DCT block from separate positions in the screen respectively, and transmits them to the following DCT transform circuit 3 as the shuffled data S2.
The DCT transform circuit 3 carries out discrete cosine transform on each DCT block data, and transmits this to the following quantization circuit 4 as a DCT data S3.
The quantization circuit 4 checks the quantization level for realizing the target rate of compression based on the data-length information which is fed back from a variable-length coding circuit 5, compresses the information volume by quantizing the DCT data S3 based on the quantization level, and then transmits this to the following variable-length coding circuit 5 as a quantized data S4. The variable-length coding circuit 5 variable-length codes the quantized data S4, generates a variable-length coded data S5 which is fixed a block-length in format, and transmits this to an error-correction outer-code circuit 6 and a delay memory 12.
An error correction outer-code is added in the error-correction outer-code circuit 6 for correcting errors generated in burst form, and moreover, in the following error-correction inner-code circuit 7, an error correction inner-code for correcting a random error, synchronous pattern, ID code, etc., are added. Then, the 8-bit parallel data is converted into the 1-bit serial data with a clock frequency 8 times that of the parallel data, and transmitted to a recording circuit 8 to generate a recording data S8. A recording current is applied to a recording head 10 mounted on a rotary drum through a rotary transformer 9, and the recording data S8 is recorded on a magnetic tape 11.
As shown in FIG. 2, in the rotary drum 28, a pair of reproducing heads 15 are mounted apart from a pair of recording heads 10 by 90 degrees, respectively. This rotary drum 28 is rotated in the direction shown by the arrow "a" while the magnetic tape 11 guided by an entrance tape guide 29A and an exit tape guide 29B, travels in the direction shown by the arrow "b", so that the magnetic tape 11 can slide on the side where the recording head 10 and the reproducing head 15 of the rotary drum 28 are arranged.
Moreover, in the reproducing system, recording and reproducing can be carried out simultaneously by immediately reproducing the recording data S8, which is recorded on the magnetic tape 11, with the reproducing head 15. That is, the reproduced data S15 which is obtained through the reproducing head 15 is inputted to a PLL circuit 18 through a rotary transformer 16 and a reproduction equalizer 17. After the clock is reproduced, the block synchronous pattern is reproduced to return the 1-bit serial data to 8-bit parallel data with a clock frequency 1/8 times in the following synchronous (SYNC) detection circuit 19, and this is transmitted to the following inner-code correction circuit 20.
In the inner-code correction circuit 20, random errors are corrected using inner-codes, and in the following outer-code correction circuit 21, burst errors are corrected using outer-codes. Then the corrected data S21 which is outputted from the outer-code correction circuit 21 is transmitted to a record assurance comparator 13 and a variable-length decoding circuit 22.
In the variable-length decoding circuit 22, variable-length decoded data S22 is obtained from the corrected data S21, and this is transmitted to a inverse quantization circuit 23 in order to carry out an inverse quantization processing. The inverse quantized data S23 is transmitted to an inverse discrete cosine transform (IDCT) circuit 24 to carry out an inverse discrete cosine transform processing corresponding to the discrete cosine transform which was conducted in the DCT transform circuit 3. The IDCT data S24 obtained in this way is transmitted to the following deshuffling circuit 25 to arrange the DCT block data in scan order, and transmitted as the deshuffled data S25 to an error correction circuit 26. If an error which exceeds the error correction limit of the error correction codes is generated, the error is corrected in the error correction circuit 26, thereby a reproduction digital video signal S26 is obtained.
FIGS. 3A to 3E show timing diagrams of the signal processing in the DVTR1. The input digital video signal S1 which is inputted for each field synchronizing at time point t1 with a vertical synchronizing signal S.sub.V (FIG. 3A), is recorded as recording data S8 (FIG. 3C) at time point t2 which is delayed for the delay period T1 of 1+1/3 fields as the signal processing time in the shuffling circuit 2, the DCT transform circuit 3, the quantization circuit 4, the variable-length coding circuit 5, the error-correction outer-coding circuit 6, the error-correction inner-coding circuit 7, and the recording circuit 8.
On the other hand, since a pair of reproducing heads 15 are mounted apart from a pair of recording heads 10 by 90 degrees respectively in the rotary drum 28, the reproduced data S15 which is obtained through the reproducing head 15 at the simultaneous recording and reproducing operation, is outputted from the reproducing head 15 at a time point t3 which is delayed from the recording data S8 for the delay period T2 of 1/6 fields, as shown in FIG. 3D.
Moreover, the reproduction digital video signal S26 which is outputted from the error correction circuit 26, is outputted at a time point t4 which is delayed from the output time point t3 of the reproduced data S15 for the delay period T3 of 1+1/2 fields as a signal processing time in the reproducing system. It means that the output video signal S26 is delayed from the time point t1 where the input digital video signal S1 is inputted to the recording system for the delay period T4 of 3 fields, and outputted from the reproducing system.
In this way, in the DVTR1, the data is delayed for the portion of signal processing time in each signal processing circuit in the recording system and the reproducing system. Therefore, the variable-length coded data S5 which is outputted from the variable-length coding circuit 5 to the delay memory 12 is delayed in the delay memory 12 for the portion of delay time required for signal processing from the error-correction outer-coding circuit 6 in the recording system to the outer-code correction circuit 21 in the reproducing system, and transmitted to a record assurance comparator 13.
Therefore, the record assurance comparator 13 inputs the variable-length coded data S5 outputted from the variable-length coding circuit 5, together with the corrected data S21 in which this variable-length coded data S5 is recorded and reproduced simultaneously to/from the magnetic tape 11 and outputted from the outer-code correction circuit 21, and compares the variable-length coded data S5 with the corrected data S21. Here, if the recording and reproducing systems operate normally and an error which exceeds the error correction limit of the error correction codes is not generated in the corrected data S21, the variable-length coded data S5 and the corrected data S21 will be the same.
Therefore, comparing the variable-length coded data S5 with the corrected data S21 one by one, the record assurance comparator 13 can carry out the recording assurance, such as the states of the operations in the recording and reproducing systems are checked, and if no abnormality occurs in the result of the check, the recording operation is continued.
In such a construction having the DVTR1 , a memory element is needed for several fields as the delay memory 13. For example, a memory having a large capacity of about 5 [Mbit] is needed for the portion of 3 fields.
Moreover, the number of circuit elements as well as the circuit board area is increased because high-speed writing and reading of the memory having a large capacity is required, and the number of high-speed memory elements and the power consumption increases due to the high-speed operation. Furthermore, there was a problem of being unable to avoid wire breakage, etc., because a number of elements were connected with a number of wires.